Job Details

Hardware Chip Verification Engineer - AI Workloads

Advertiser
eclaro
Location
San Jose, California, United States
Rate
-
Task Description The candidate must be able to perform the following tasks at start date Collaborate with logic and verification team members in a dynamic environment Create detailed test plans to verify complex digital blocks from functional specifications Work closely with design engineers to identify coverage holes and deliver functionally correct blocks Create coverage measures and identify corner cases Create UVM-based test benches from scratch Generate UVM-based test environments for logic designers Create functional coverage in SystemVerilog Setup, maintain, and operate batch regression environment Simulate and debug SystemVerilog designs Run formal verification tools Document and support test plans reviews Setup and maintain verification tools in linux Required skillsLevel of Experience Experience with SystemVerilog with assertions, UVM test benches Experience with using Vendor Verification IP, including PCIe ViP Experience with chip level verification of PCIe Endpoints Experience with C and C++ and scripting languages Experience with linux environment Familiarity with industry standard ASIC EDA tools, including logic simulators, and debuggers Familiarity with formal verification and linters Nice to have skills At least 3 year experience in any of the following SystemVerilog, UVM, SystemC, Verilog or VHDL At least 1 year in C++Python and Object Oriented Methodology Experience with DFT Experience with the simulation and verification of a system including 3rd party IP Experience using CadenceDenali ViP

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